1. Field of the Invention
The present invention relates to ESD protection, and more particularly, to an ESD detection method and related method thereof for ESD protecting circuits applying electronic elements complying with a nano scale process.
2. Description of the Prior Art
The development of semiconductor processes is ongoing. As one skilled in the art will appreciate, a modern chip is allowed to have a plurality of various electronic circuits configured within. Moreover, electronic pads are disposed on each chip for receiving an external power source (e.g., a bias current/voltage) and for exchanging data with other external electronic circuits/chips. For instance, a chip has power pads implemented for receiving bias voltage(s), and signal pads for receiving input signals and output signals. The above-mentioned signal pads are named I/O pads.
That is, the chip is connected with external electronic circuits or chips via the aforementioned electronic pads. However, during processes such as packaging, testing, delivering, and manufacturing, etc, the chip can be damaged or interfered with by the external static electricity via the electronic pads (power pads and signal pads) of the chip. External static electricity easily damages inner circuits in a chip via the electronic pads, and the unwanted condition causing the inner circuits of a chip to be damaged or interfered with is called electrostatic discharge (ESD). Providing excellent ESD protection circuits for protecting modern integrated electronic circuits (e.g., a chip) from being damaged by the unwanted ESD noise is an important issue for designers.
In general, ESD protection circuits are disposed between two pads of the chips. The said ESD protection circuits are basically implemented for providing a bypass path with a low equivalent impedance value for bypassing the ESD current. In this way, the ESD current passes through the ESD protection circuits rather than passes through inner circuits of the chip, thereby protecting the inner circuits of the chip from being damaged or interfered with by unwanted ESD events or current.
A conventional ESD protection circuit mainly includes an ESD transition detection circuit and a power clamp circuit. FIG. 1 is a diagram illustrating a conventional ESD protection circuit. As shown in FIG. 1, an ESD protection circuit 100 includes an ESD detection circuit 110 and a power clamp circuit 120. The ESD protection circuit 100 is coupled between a power pad VDD and a power pad VSS. The power pad VDD here serves as a power source while the power pad VSS serves as a ground terminal.
Throughout the development of semiconductor elements, applying transistors having a smaller form factor has been a basic requirement of circuit design. As a result of the development of semiconductor processes from 18 micrometer semiconductors, to 13 micrometer semiconductors through to 65 nanometer semiconductors the thicknesses of gate oxides of semiconductor elements have been reduced. Further, for decreasing the required circuit area and cost, an ESD detection circuit of the ESD protection circuit applying a metal oxide semiconductor (MOS) capacitor complying with a nano scale process rather than a traditional capacitor element has been used.
Please refer to FIG. 2. FIG. 2 is a diagram illustrating a conventional ESD detection circuit 200. As shown in FIG. 2, an ESD detection circuit 200 includes a resistor-capacitor circuit 210 and an inverter 220. The ESD detection circuit 200 is implemented for generating an ESD trigger signal Itrigger. When the ESD detection circuit 200 detects an ESD event, the ESD trigger signal Itrigger output from the ESD detection circuit 200 will turn from a low logic level (logic “0”) into a high logic level (logic “1”) for enabling the following ESD protecting operations (e.g., the operation of a power clamp circuit). The ESD detection circuit 200 is coupled between a first power pad VDD and a second power pad VSS. The resistor-capacitor circuit 210 includes an impedance component 211 and a MOS capacitor 212, and the inverter 220 includes a NMOS transistor 222 and a PMOS transistor 221.
However, a gate oxide thickness of a MOS capacitor complying with the advanced nano scale process is thinner than that of a MOS capacitor complying with a conventional process and this thereby leads to the ESD detection circuit with excessive leakage current. The unwanted excessive leakage current probably makes the ESD protection circuit 200 to operate in error. For instance, a malfunction of the ESD protection circuit occurs due to the leakage current to thereby induce the ESD protection circuit to output the ESD trigger signal Itrigger incorrectly and result in even more serious leakage current.
In most cases, leakage currents of the ESD protection circuit are due to the thin gate oxide thickness of the MOS capacitor 212 in the resistor-capacitor circuit 210 since the MOS capacitor 212 usually complies with a nano scale process. Excessive tunneling current occurs owing to the thin gate oxide thickness of the MOS capacitor 212, and the tunneling current pulls down a voltage level on a contact terminal 230 (i.e., a terminal couples to a control terminal of the PMOS transistor 221 and a control terminal of the NMOS transistor 222) to lead to the voltage level on the contact terminal 230 being lower than a voltage level on a first connection terminal of the PMOS transistor 221, wherein the first connection terminal of the PMOS transistor 221 is coupled to the power pad VDD. The PMOS transistor 221 hence turns on and makes the ESD trigger signal Itrigger convert from a low logic level into a high logic level in error, resulting in the following ESD protection components (e.g., clamp circuit) to operate erroneously.
In short, when no ESD event occurs, the said tunneling current of the MOS capacitor 212 pulls down the voltage level on the terminal 230 and causes the inverter 220 to fail to keep closed (turn off) correctly, thereby bringing out excessive unwanted leakage current.
Therefore, there is a need for providing an ESD detection circuit to eliminate the leakage current of the ESD protection circuits that apply electronic components of a nano scale process, especially to eliminate the unwanted leakage current of the ESD protecting circuit when no ESD event happens.